1. Field of the Invention
Embodiments of the invention are applicable to any high-performance IC requiring production speed binning, for which it is possible to accurately measure a large and distributed sample of timing paths, for example, if the design implements full-scan and supports at-speed path-delay AC scan testing, or other design for test (DFT) methodology.
2. Description of the Related Art
Many types of integrated circuits (ICs) are offered in a variety of performance grades. Vendors are able to charge a premium for a higher performance device relative to a lower performance device. See, for example, K. Brand et al., Speed Clustering of Integrated Circuits, Proceedings of the International Test Conference, 2004, pp. 1128-1137; B. Cory et al., Speed Binning with Path Delay Test in 150-nm Technology, IEEE Design and Test of Computers, September-October 2003, pp. 41-45; and J. Zeng et al., On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design, Proceedings of the International Test Conference, 2004, pp. 31-37.
For example, a chip vendor can offer the identical microprocessor for sale in two or more performance grades, where the only difference among the parts is the guaranteed maximum operating frequency (fmax) specified for the grades. Generally, the part with the higher guaranteed fmax can be sold at a higher cost. However, accurately measuring the functional fmax of an integrated circuit during production test is relatively difficult.
Localized manufacturing defects and parametric variations can affect the fmax of a device. See, for example, K. Brand et al., Speed Clustering of Integrated Circuits, Proceedings of the International Test Conference, 2004, pp. 1128-1137.
Localized manufacturing defects such as relatively resistive vias or pinholes in conductors can cause a particular path to be significantly slower than predicted by design. If the delay through the path results in the signal reaching its target after the clock edge on which it is sampled, incorrect data will be sampled and the device will not operate properly. Hence the clock should be slowed down for proper device operation, i.e., the fmax of the device has been degraded. These defects are typically considered to be a reliability hazard as they can degrade over the lifetime of the product causing an early life failure in the end customer application.
Parametric variations can cause paths to be significantly slower (or faster) than predicted by design, resulting in correspondingly lower or higher fmax of a device. Given the number of transistors on a deep sub-micron microprocessor, there can be on-die process variations resulting in paths within a single device varying unpredictably relative to one another, as well as process variations across a wafer resulting in all paths of some die varying relative to other die, and likewise process variations between wafers and between wafer lots. Devices with fmax variation due to process or parametric variation are typically not considered to be defective and are relatively good candidates for speed-binning.
Critical timing paths or critical paths are those paths within an integrated circuit with relatively long delays that can limit the maximum operating frequency fmax associated with the integrated circuit. The problem of obtaining sufficient coverage of critical timing paths for accurate fmax determination during production test is expected to get worse over time as deep sub-micron design and fabrication processes continue to be refined. This is because as a design goal, path timing would be matched among many paths, such that many transitions would reach their destination simultaneously, and no single path would limit the clock frequency. With advances in layout tools, and the ability to trade off speed versus power for individual gates in multi-Vt processes, designs are moving towards this goal, and the overall distribution of path delays is typically getting narrower. This results in a plethora of possible critical timing paths ultimately determining the fmax for an individual IC, with the actual critical timing path of a specific die being a function of intra-die random process variations that is difficult to control or measure. Consequently there is an increased risk with any kind of fmax testing that “the” critical timing path for a particular device is not correctly exercised, resulting in the particular device being incorrectly placed in a higher performance bin, leading to failure in a customer application, i.e., production test escapes.
Common Test Methods for Speed Binning
Functional Test
Historically, speed-binning has been accomplished by constructing functional test patterns or “vectors” for automated test equipment (ATE) and attempting to emulate normal device operation in the production test environment. The functional vectors would then be run on a pass/fail basis at various frequencies to determine the fmax grade associated with each individual device.
The use of functional vectors on ATE is suboptimal for many reasons including: cost of test development, cost of production test, and long-term impact on device profitability. See, for example, B. Cory et al., Speed Binning with Path Delay Test in 150-nm Technology, IEEE Design and Test of Computers, September-October 2003, pp. 41-45, or J. Zeng et al., On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design, Proceedings of the International Test Conference, 2004, pp. 31-37.
For example, test development cost can be driven by the engineering challenges of guaranteeing test coverage of critical timing paths, “cyclizing” test bench stimulus and device response to fit the constraints of ATE performance, and wasted resources due to debug time after prototype silicon is available. These problems are exacerbated with deep sub-micron system-on-chip (SOC) devices with large numbers of critical timing paths, multiple asynchronous interfaces and non-deterministic device output even for defect-free samples due to, for example, signals crossing (multiple) asynchronous clock domain boundaries, phase/frequency locked loop (PLL) sourced core clocks operating with non-deterministic phase relative to device input clocks, and the like.
Production test costs due to functional vectors can be driven by the need for relatively expensive high performance ATE systems that are capable of generating the high-speed signals used for functional stimulation of the device under test (DUT), that implement solutions for working around the problem of non-deterministic (i.e., unpredictable) DUT output signals, and that can manage the measurement challenges of placing signal edges with picosecond (ps) resolution and repeatability.
Long-term impact on device profitability comes from the lose-lose tradeoff of yield loss versus risk of specification violations and customer returns, along with the risk of test escapes due to less than 100% at-speed coverage of critical timing paths. For example, if test limits are set conservatively to guard against ATE inaccuracy, some parts will typically be down-binned into a lower speed grade (yield loss) than they are capable of performing, resulting in reduced revenue. If test limits are set aggressively to minimize yield loss, then some parts will typically be up-binned into a higher speed grade than they are capable of performing, resulting in potential failure in a customer application. This issue can be compounded by the difficulty in guaranteeing that the functional vectors used for speed-binning properly exercise the worst-case path(s) on all parts. For example, it is possible that the speed grade determined during production test is valid for the functional modes tested, but in a particular customer application, a path which was not speed tested dominates, which results in a field failure and customer return.
On-Die Process Monitor
Many ICs include circuitry on-die or in the wafer scribe channels to permit measurement of manufacturing process parameters. See, for example, K. Brand et al., Speed Clustering of Integrated Circuits, Proceedings of the International Test Conference, 2004, pp. 1128-1137, U.S. Pat. No. 5,039,939 to Dick, et al., or U.S. Patent Application Publication No. 2004/0133830A1 by Lee. This can include explicit test structures to directly measure transistor voltage and current characteristics, or inherently process-sensitive circuits such as a free-running ring oscillator with an output frequency that can provide a direct measurement of the timing delay through the logic forming the ring. In principle, if process parameters are sufficiently uniform over the entire die, then direct measurements of the process monitors should permit estimation of the fmax of the DUT.
The foregoing correlation is typically not sufficiently robust to be used as the sole determinant for speed-binning a device. See, for example, K. Brand et al., Speed Clustering of Integrated Circuits, Proceedings of the International Test Conference, 2004, pp. 1128-1137. This is not unexpected, given on-die process Variation and difficulties in obtaining sufficient test coverage of critical timing paths.
While process monitors can provide information on the average process speed for a given device, they generally provide insufficient information on the relatively localized intra-die process variations that ultimately determine which path on a device limits the functional fmax.
At-Speed Structural Test
The challenges associated with functional vectors have resulted in an industry-wide shift towards design-for-test (DFT), which focuses on structural testing rather than functional testing and thereby enabling the use of much lower performance, lower cost ATE. Scan testing using the stuck-at fault model to detect gross manufacturing defects (“DC scan”) has been a standard IC structural test for many years. More recently “AC scan” methods have become popular for detecting defects that result in degraded performance, but do not behave like a hard “stuck-at” fault. While many IC scan test methods exist, a popular implementation of AC scan is based on using scan chains to configure the memory elements, such as flip-flops or latches, in an IC at low speed prior to enabling a burst of two or more full-rate clock pulses to exercise combinational logic between the flip-flops at full speed. The results are then shifted out of the device again at low speed using the scan chains.
AC scan test coverage is typically computed by referring to one of two fault models. The transition fault model refers to the ability to detect a slow-to-rise or slow-to-fall output on any given gate. The transition fault model can be viewed as an extension to the stuck-at model (an infinitely slow transition fault being equivalent to a stuck-at fault), and is generally targeted at manufacturing defect detection. The path-delay fault model refers to the ability to detect a delay anywhere in a path from one scanned memory element to another. The path-delay fault model attempts to exercise specific logical paths and is generally targeted at testing paths with the least amount of slack to the target clock period (“critical timing paths”) for specification violations that would result in a degraded fmax. See, for example, B. Cory et al., Speed Binning with Path Delay Test in 150-nm Technology, IEEE Design and Test of Computers, September-October 2003, pp. 41-45 or J. Zeng et al., On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design, Proceedings of the International Test Conference, 2004, pp. 31-37.
AC scan vectors have a large advantage over functional vectors in that the test patterns can be generated automatically with, for example, commercial automated test pattern generation (ATPG) tools such as Mentor's FastScan tool, resulting in short development and debug cycles with completely deterministic test coverage. See, for example, B. Cory et al., Speed Binning with Path Delay Test in 150-nm Technology, IEEE Design and Test of Computers, September-October 2003, pp. 41-45.
Unfortunately, there are many problems in correlating fmax measured using AC scan vectors with fmax measured using functional vectors and/or with fmax measured in a system environment. See, for example, J. Zeng et al., On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design, Proceedings of the International Test Conference, 2004, pp. 31-37. The problems are generally attributed to the difficulty in obtaining relatively high path delay fault coverage of critical timing paths, particularly in microprocessors with embedded memory arrays. As with the other methods discussed, failure to provide 100% coverage of all possible critical timing paths can result in a risk of placing devices in a higher speed-bin than is appropriate, leading to field failures and customer returns.
Measurement of Randomly Distributed Variables
A basic understanding of statistical concepts is useful to understand the concepts presented herein. For example, see U.S. Patent Application Publication No. 2004/0133830A1 by Lee.
A normal distribution can be fully characterized by its mean and standard deviation. In practice, actual measurement data is often analyzed assuming that the data fits a normally-distributed population. By obtaining a sufficient number of measurements on samples from the distribution, it is possible to determine both the mean and standard deviation to any arbitrary confidence level, where both “sufficient number” and “confidence level” are well-defined, quantifiable values. Typically, more measurements provide better confidence that the mean and standard deviation have been accurately determined.
An approximately normally-distributed population of data does not have a well-defined peak-to-peak range. An attempt to measure a peak-to-peak range-will typically not yield a reproducible result, regardless of sample size. Typically, more measurements simply result in more opportunities for measuring an outlier value and no improved knowledge of the accuracy or repeatability of the peak-to-peak measurement.
Hence, for measurements on a normally-distributed parameter, it is much more useful to attempt to accurately determine the mean and the standard deviation, and to use these values to make statistical statements about the likelihood of observing a given value on any subsequent measurement, rather than trying to measure the peak value of the distribution directly. For example, after the mean and the standard deviation have been measured, less than 2 observations in 1000 are expected to be more than 3 standard deviations greater than the mean (single-limit calculation, i.e., integration from—infinity to +3 sigma). A single-limit calculation is appropriate for specifications like the guaranteed maximum operating frequency (fmax), where a device need only be faster than a specification. For other specifications where there is an upper and a lower range, a double-limit calculation may be appropriate. Likewise and particularly relevant to manufacturing, given a specification that is 4.5 standard deviations from the mean, 3 or less specification violations (defects) per million (DPM) devices can be expected.
This analysis can be generalized to parameters that are not distributed approximately normally, provided the distribution is well defined and known. In short, given any fully characterized distribution, it is typically possible to make statistically valid statements about the probability of finding an occurrence of a parameter beyond a given limit.